In recent years, application specific integrated circuits (ASIC) and other semiconductor integrated circuits have become increasingly complex and smaller in size. Signals of different types of clocks are being sent and received between the semiconductor integrated circuits (below, “IC”). Further, the bidirectional buses employed for sending and receiving signals between ICs switch the bus direction to the output or input direction at the time of sending or receiving signals, so the sending side and receiving side ICs have to constantly recognize the bus direction.
Using FIG. 5, the configuration of a conventional bidirectional bus will be explained. A master side IC instructing the bus direction sends a direction signal instructing the input direction or output direction to the slave side IC whereby the direction of the bidirectional bus is recognized between the two ICs. Further, the bus for transmitting the direction signal is duplexed to avoid errors from occurring in the recognition of the bus direction between the two ICs when the direction signal is clipped (bus fight).
Using FIG. 6, a flow chart of the signals sent between conventional bidirectional buses will be explained. In the past, a slave IC connected to a master IC instructing a bus direction and receiving a direction signal sent from the master IC confirms data without an input clock and input data for a predetermined time after the bus direction for the clock signal and data signal switches from the output direction to the input direction, so mistaken recognition of data and abnormal data accompanying it occur. For this reason, the conventional slave IC, as illustrated in FIG. 5, is provided with a signal suppression circuit for suppressing an error check for abnormal data occurring when the bus direction of the IC is switched from the output direction to the input direction, a time monitoring circuit for starting the error check after a certain time, etc.
Note that a circuit has been proposed for controlling the sending side and receiving side systems so that the directions of the bidirectional buffers do not become the same. In the proposed art, to prevent the directions of the bidirectional buffers of the sending side and receiving side systems from becoming the same, a control circuit for switching the directions of the bidirectional buffers is used to switch the receiving side bidirectional buffer before the sending side bidirectional buffer to a direction with its back to the sending side bidirectional buffer at the time of sending a data signal.
Japanese Laid-open Patent Publications No. S63-093220 and S57-071034 are known.